WDPROTECT=CHANGE, WDRESET=NORESET, WDEN=STOP
Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer.
| WDEN | Watchdog enable bit. This bit is Set Only. See Table 652. 0 (STOP): The watchdog timer is stopped. 1 (RUN): The watchdog timer is running. |
| WDRESET | Watchdog reset enable bit. This bit is Set Only. See Table 652. 0 (NORESET): A watchdog timeout will not cause a chip reset. 1 (RESET): A watchdog timeout will cause a chip reset. |
| WDTOF | Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. See Section WDTOF. |
| WDINT | Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. See Section WDINT. |
| WDPROTECT | Watchdog update mode. This bit is Set Only. See Section WDPROTECT. 0 (CHANGE): The watchdog reload value (WDTC) can be changed at any time. 1 (CHANGE_W_CNT): The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |